1. Field of the Invention
The present invention relates to a manufacturing process for a semiconductor device and, more particularly, to a manufacturing process for a semiconductor device in which trenches are formed in the surface of a substrate; after which an insulating film is formed over the surface of the substrate by bias ECRCVD so as to fill up the trenches; etching so as to level the insulating film so as to expand the width of the grooves which are formed in portions of the insulating film formed in regions (hereinafter referred to as "active regions") other than those portions which correspond to the trenches (hereinafter referred to as "trench regions"); and then removing those portions of the insulating film which are formed in the active regions after masking the portions of the insulating film which fill up the trenches. The invention also relates to a bias ECRCVD apparatus for manufacturing the semiconductor device.
2. Description of Related Art
It is a common practice to isolate the component elements of semiconductor devices, such as ICs, LSls and VLSls, by a selectively oxidized film (LOCOS) which is formed by selectively oxidizing the surface of the semiconductor substrate. However, the use of the selectively oxidized film for isolating the elements from each other causes the formation of bird's beaks which increase the critical dimension which increases the size of devices. Therefore, a trench-isolation method, which does not form any bird's beak and allows the devices to be very small is desirable.
A trench-isolation method, such as disclosed in Japanese Patent Laid-open (Kokai) No. 57-176742 or 60-53045, forms trenches in the surface of a semiconductor substrate, and fills up the trenches with SiO.sub.2 which is deposited by bias ECRCVD. FIGS. 6A to 6E are sectional views showing the steps of a trench-isolation method, by way of example, employing bias ECRCVD. Trenches formed in the surface of a semiconductor substrate are filled up with an insulating film through the following steps of the trench-isolation method.
(A) As shown in FIG. 6A, trenches 2 are formed in the surface of a semiconductor substrate 1, and then an insulating film 3, i.e., a SiO.sub.2 film, is formed over the surface of the semiconductor substrate 1 by bias ECRCVD so that the trenches 2 are filled up with the insulating film 3. The thickness of the insulating film 3 is substantially equal to the depth of the trenches 2. Portions 3a of the insulating film 3 are formed on the active regions on the surface of the semiconductor substrate 1.
(B) As shown in FIG. 6B, the portions 3a of the insulating film which are formed by bias ECRCVD are etched laterally as indicated by arrow by lateral leveling etching so that flat portions are not etched. The width of the grooves formed in the trench regions which corresponds to the trenches 2 in the portions 3a of the insulating film 3 is expanded by lateral leveling etching so as to facilitate masking the trenches 2 with a resist film.
(C) As shown in FIG. 6C, the portions of the insulating film 3 which are formed in the trenches 2 are masked with a resist film 4 by a process which uses a film of a resist material which is applied to the insulating film 3 through a photolithographic process.
(D) As shown in FIG. 6D, the portions 3a of the insulating film 3 which are formed in the active regions are removed by anisotropic etching using the masks of the resist film 4.
(E) As shown in FIG. 6E, the resist film 4 is then removed.
The trench-isolation method effectively utilizes the specific properties of ECRCVD so that the etching rate is smaller than the deposition rate, and the etching rate of the inclined surfaces which are inclined relative to the flat surface of the semiconductor substrate is larger than the deposition rate and is a substantial improvement in that the trench-isolation method is able to fill up comparatively narrow trenches and comparatively wide trenches with insulating films which have substantially the same thickness. Since the ordinary CVD process has good step coverage, the ordinary CVD process tends to form thick insulating films in narrow trenches and thin insulating films in wide trenches, whereas the bias ECRCVD process has less tendency to form insulating films in such a manner.
FIGS. 6A to 6E show an ideal configuration of the insulating film in the successive steps of the bias ECRCVD process. However, in a practical bias ECRCVD process, the side surfaces of the portions 3a of the insulating film formed in the active regions are curved slopes 5 as shown in FIG. 7 at a stage after the lateral leveling etching step (FIG. 6B), because the inclination of the slopes 5 to the surface of the substrate 1 is nearly zero as shown, and hence the slopes 5 are scarcely etched during lateral leveling etching. Accordingly, if the portions 3a of the insulating film 3 which are formed in the active regions and which have the slopes 5a in their side surfaces are etched by using the masks of the resist film 4, fragments of the portions 3a of the insulating film 3 will remain under the masks of the resist film 4 as shown in FIG. 8A when an anisotropic etching process is employed or portions of the insulating film 3 are formed in the trenches 2 are etched so as to form recesses 5b such as shown in FIG. 8B when an isotropic etching process is employed. Such portions of the insulating film reduce the dielectric strength of the isolation film.
When the portions 3a of the insulating film 3 are etched by anisotropic etching so as to secure spaces for forming the masks of the resist film 4, the portions of the insulating film which are formed in the trenches 2 are removed as shown in FIG. 9 and hence the trenches 2 are unsatisfactorily filled with the insulating film which reduces the dielectric strength of the isolation film.